New JEDEC JESD204A high speed serial data interface standard

[J.B.W.Webber <J.B.W.Webber@xxxxxxxxxx>]

Hi,
I keep an eye on the opportunities offered by FPGAs for low cost multiple processor assemblies ....
(A while back, forwarded details on a legacy Cray 1 design on a single FPGA). 

A key component is the interprocessor interface, currently LVDS parallel interface, running at a maximum
Of 1 Gbps per LVDS pair of wires. Offered by most FPGA vendors including Altera and Xilinx.
(LVDS - Low Voltage Differential Signalling)

A new JEDEC JESD204A high speed serial data interface standard offers byte wide transfers over a pair of wires - 10 bits per byte gives in-built clock recovery, at up to 312.5 MBytes/s. Soon to be offered by Xilinx - and no doubt Altera. http://i.cmpnet.com/planetanalog/2011/03/C0756.pdf 
Cheers,
	Beau Webber