RE: Unclocked logic / delay insensitive circuits

["Campbell, John" <John.Campbell@xxxxxxxxxxxxxx>]

Marcel, Barry, Others


> If it is a success, one could ask Altera, or some other
> FPGA manufacturer to develop FPGAs optimized for
> non-clocked systems...
> 
> 
	It seems to me that it would be an ideal marriage.  As
	Barry mentioned in another thread (rewriting CSP
	processes), the difficulty of distributing a clock to all
	portions of a chip with acceptable skew has folks
	talking about local regions with a common clock and
	message passing between them.  

	I believe that it would be a Good Thing to have a compiler
	that generates synchronous logic where it works and 
	automatically ties such regions together with asynchronous
	logic.  You could tie multiple chips together that way also,
	essentially removing chip capacity limitations.

	At least one FPGA manufacturer, Xilinx, has shown 
	some willingness to build specialized devices because
	academia was interested.  The 6400 series was in
	response to the Reconfigurable Computing community
	making an issue of long reconfiguration times of standard
	chips. (It didn't succeed commercially, unfortunately.)

	-jc